- P-ISSN1738-6764
- E-ISSN2093-7504
- KCI
ISSN : 1738-6764
Design of a DI model-based Content Addressable Memory for Asynchronous Cache
Design of a DI model-based Content Addressable Memory for Asynchronous Cache
INTERNATIONAL JOURNAL OF CONTENTS / INTERNATIONAL JOURNAL OF CONTENTS, (P)1738-6764; (E)2093-7504
2009, v.5 no.2, pp.53-58
https://doi.org/10.5392/ijoc.2009.5.2.053
Battogtokh, Jigjidsuren
(Department of Computer and Communication Engineering, Chungbuk National University)
Cho, Kyoung-Rok (Department of Computer and Communication Engineering, Chungbuk National University)
Cho, Kyoung-Rok (Department of Computer and Communication Engineering, Chungbuk National University)
Battogtokh, Jigjidsuren,
&
Cho, Kyoung-Rok.
(2009). Design of a DI model-based Content Addressable Memory for Asynchronous Cache. , 5(2), 53-58, https://doi.org/10.5392/ijoc.2009.5.2.053
Abstract
This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.
- keywords
- Cache, CAM, DCVSL, completion signal
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